Cellular systems are used to offer wireless telephony and data services to their users. The new cellular standard developed by the 3rd generation partnership program (3GPP) called Long Term Evolution (LTE) offers unprecedented data rates and unprecedented shortest latency to the end customer while at the same time promising a high spectral capacity to the network operator. This allows network operators to make best use of the available spectrum. Spectrum efficiency is achieved by a plurality of modes such as downlink Tx diversity, beam forming, and spatial multiplexing. Those modes are partly signaled within the physical layer as well as by higher protocol layers.
The classical modem architecture typically consists of a series of digital signal processing blocks or segments thereof that are connected together in a fixed way. A processor is used to control the data flow and is partly used for low rate signal processing. The exchange of data can be realized through a shared memory. As bit width and signal processing hardware are tailored to the application's requirements, purely hardware based modems can be implemented very power efficiently while minimizing required silicon area. The disadvantage of such architectures is their inflexibility. Such modems are designed for one particular standard and for one set of particular algorithms. Modifications in the algorithms which may be necessary to overcome some limitations that only become visible in the field, almost always require modifications in hardware that are both time consuming and costly.
More recently, Software Defined Radio (SDR) architectures have been proposed. SDRs are based on one or multiple powerful digital signal processors (DSPs) onto which the various signal processing tasks are mapped. As the DSPs are relatively general purpose, the architecture is very flexible. In SDR architectures, the signal processing is implemented in software. Disadvantages of those architectures, however, are:
High silicon cost compared to hard-wired solution, as the signal processors bit width of the data path and the memory (storage) cannot be tailored to the algorithms to the extend hard wired logic can. Traditional DSPs for signal processing support bit widths of 16 bit, 8 bit, and 32 bit. Some support 24 bit. Bit widths like 9 bit, 10 bit, 6 bit that are often sufficient to reach the required performance, are not supported.
Also, signal processors carry a relatively large overhead for program control, address generation, debugging support, and general purpose instructions out of which only a subset is actually used. In order to maximize the hardware utilization, as many algorithms as possible are loaded on those DSPs. This approach brings additional drawbacks:
The required clock frequency rises, increasing the power consumption of the IC, as more logic (e.g. additional pipeline stages) is required to achieve those speeds. The high speeds in the processing hardware imply memory bandwidth limitations. Faster memories become required. Faster memories, however, consume substantially more power than power optimized memories that tend to be slower.
Algorithms run at different rates and are not always synchronized with one another. Mapping those algorithms on a single processor requires careful task management with different prioritization and resource management. The number of different cases that need to be considered grows with the number of states. Testing effort to reach certain stability is high compared to an approach where algorithms are implemented on separate hardware.
Modern modem standards require multiple tasks that are not fully synchronized, and lengths of processing operations are data dependent, such as:
Downlink control channel receive including decoding
Cell search
Parameter and channel estimation
Downlink data channel receive
Uplink coding modulation.
That is why scheduling of such tasks is complex and cannot be known a priori.
To cope with these problems it is known to implement real-time operating systems on very fast processors, see e.g. U.S. Pat. No. 7,415,595B2, by Tell et al. Such processors, however, involve high clock rates and therefore have the main drawback to be power hungry.
What is needed, therefore, is a modem architecture which allows to realize a low power, low size wireless communication device.